The present disclosure relates to a method of generating a clock operating at a rising edge and more particularly, to a method of generating a clock signal in a simple structure at high precision.
The clock signal is a square wave signal in which logic states ‘1’ and ‘0’ are regularly represented. In a general system, a clock has a certain duty ratio and the system is synchronized with the clock to process various signals.
A clock generation device may be a device that generates a clock having a certain duty ratio to be used in a system and may include a PLL circuit. However, the PLL circuit has limitations in that its logic is complex and it needs many transistors.
FIG. 1 shows how to provide a system needing a clock having a certain duty ratio with a clock.
Referring to FIG. 1, a PLL circuit 11 adjusts an input clock and generates an output clock suitable for a system 12. In this case, the PLL circuit may be implemented in both hardware and software, and since a hardware PLL structure has high precision but is complex in logic structure, it needs many transistors. On the contrary, a software-type PLL structure has a limitation in that it is difficult to ensure the precision of an output clock.
Also, in order to provide a system with a clock having a certain duty ratio, a clock adjustment by the PLL circuit is needed but a system that operates only at the rising edge or falling edge of the clock does not need a PLL circuit having a complex structure. Thus, in a system that needs a clock without a certain duty ratio, generating the clock precisely is needed.